Embodiments of the present invention relate to the formation of a passivation layer comprising silicon nitride on high aspect ratio features used to fabricate electronic circuits on substrates.
Electronic circuits, such as integrated, display, memory, power, and photovoltaic circuits, are becoming ever denser and more complex. The dimensions of the features of these circuits are becoming smaller to allow greater aerial densities across the substrate. These features include connector bumps, interconnects, semiconducting or oxide features, gates, electrodes, resistors, vias and many others. The aspect ratio of such features increases as the width or horizontal dimension of the features becomes smaller because the vertical dimension of the features has to be larger to provide the same cross-sectional area. The aspect ratio, which is the ratio of the height to the width of the feature, is a particular problem when the features are covered by a passivation layer to protect or electrically isolate the features.
As an example, a passivation layer 10 can be used to cover features 12, as shown in FIGS. 1A and 1B, to prevent oxidation of the metal-containing surface of the features 12 before or during coating of the features with other materials. The features 12 include interconnects 13 (FIG. 1A) and connector bumps 14 (FIG. 1B). Interconnects 13 are used to connect the active and passive devices on a substrate 15. Connector bumps 14 are used, for example, in flip chip packaging to serve as interconnection points between an integrated circuit chip and the external environment. The connector bumps 14 are formed on bonding pads to allow the die to be “flipped” circuit-upside- down and directly soldered to a connector or circuit board, thereby saving the time and expense of conventional wire bonds and foil connectors. Both the interconnects 13 and connector bumps 14 are covered by a passivation layer 10.
However, as the aspect ratio of the interconnects 13 or connector bumps 14 increases to values above 0.2, it becomes increasingly difficult to deposit a continuous, conformal, and substantially defect-free passivation layer 10 around the features 12, especially the re-entrant corners 17 of the features. Referring to FIG. 1A, the passivation layer 10 forms defects 11, such as the seams 16, which split open the passivation layer 10 at the corners 17 of the interconnects 13. The passivation layer 10 on the connector bumps 14 can also form seams 16 at the corners 17 around the base of the connector bumps 14.
The seam problem is often aggravated by the geometrical elements of the re-entrant corners 17 in chip packaging, re-distribution layers (RDL), or through-silicon-via (TSV) copper or tungsten vias. For example, high aspect ratio features 12 such as silicon vias 18, as shown in FIG. 1C, comprise apertures formed through a dielectric layer 19, which are filled with an electrical conductive material to form a connection between an underlying feature such as an interconnect 13 and overlying feature such as a connector bump 14. When the silicon via 18 and overlying connector bump 14 are coated with a passivation layer 10, seams 16 often occur at the re-entrant corners 17 formed at the intersection of the passivation layer 10 with the connector bump 14 and the silicon via 18. Still another example of high aspect ratio features 12 comprises oxide structures (not shown) covered with a passivation layer 10. Oxide structures can include silicon dioxide containing structures, such as oxide liner layers formed in through-silicon vias, or oxide layers formed on top of the copper pillars of through-silicon-vias which allow revealing the via connection at the backside of the substrate. Again, defects 11 form in the passivation layer 10 covering such features 12.
The defects 11 within the passivation layers 10 at regions of the features 12 which have a complex geometry, especially with re-entrant corners 17 that have sharp edges and angles, can also be of other types such as micro-cracks, hairline cracks, and still others. However, it is not apparent how to form features 12 with these high aspect ratios and maintain the geometry and other dimensions of these features, while still preventing defects from occurring in such passivation layers 10.
Thus, for various reasons that include these and other deficiencies, and despite the development of various methods of depositing passivation layers around features, further improvements in the deposition of passivation layers are continuously being sought.